A significant trend throughout IC development has been to reduce the size of the components of the IC's. As the size is reduced, the performance requirements of the materials of the components become more stringent. For CMOS devices (e.g. CMOS transistors) in particular, increased performance requirements have generally been met by aggressively scaling the thickness of the gate dielectric and the length of the channel of the transistors. As continued attempts have been made to scale down CMOS technology, however, the performance requirements for the CMOS devices have proven so stringent that scaling of either the gate dielectric and/or the channel length has become a very difficult and/or impractical solution for meeting the high performance requirements.
A gate dielectric thickness of about ten Angstroms and smaller is anticipated in next generation CMOS devices. Such thin gate dielectrics face high gate leakage current, which is detrimental to device performance and overall power consumption.
It has been suggested to use dielectric materials having a dielectric constant (K) in a range of about 7 to 30 as the gate dielectric for CMOS devices. Such a range for K is considerably larger than that for silicon dioxide (K=3.9), which is commonly used as the gate dielectric. Such higher-K dielectric materials have the potential to reduce gate leakage current and thus enable much thinner gate dielectric layers for the smaller dimensions required for new CMOS devices.
However, the higher-K dielectric materials have several limitations that have made it difficult to incorporate these materials into CMOS devices. For instance, the processes for forming the higher-K dielectric materials are generally not compatible with conventional CMOS fabrication processes. Therefore, incorporation of such materials into CMOS devices can require significant changes to the CMOS fabrication processes, which can significantly affect the cost of the resulting CMOS devices.
Additionally, the higher-K dielectric materials do not form a good interface with the silicon-based materials onto which the dielectric material must be deposited. Problems thus arise at the interface between the higher-K dielectric material and the substrate and gate electrode. For example, high interface traps may be created between the material layers (especially between the gate dielectric and the substrate). Also, channel carrier mobility may be degraded by the higher-K dielectric materials. Additionally, the higher-K dielectric materials have problems with fixed dielectric charges and thermal stability. Furthermore, the presence of the higher-K dielectric materials may limit the temperature at which further processing may be performed.
To meet the increased performance requirements of the smaller CMOS devices, it has also been suggested to increase the mobility of the carriers in the channel region. For example, strained-Silicon (“strained-Si” or “SSI”) may be incorporated into the channel region, since strained-Si is known to have greater carrier mobility characteristics than does the silicon that has been more commonly used in the channel region of CMOS devices. (K. Rim, S. Koester, M. Hargrove, J. Chu, P. M. Mooney, J. Ott, T. Kanarsky, P. Ronsheim, M. Ieong, A. Grill, and H.-S. P. Wong, “Strained-Si NMOSFETs for High Performance CMOS Technology,” 2001 Symposium on VLSI Technology Digest of Technical Papers, 2001, p. 59.) Additionally, strained silicon carbide (“strained-SiC”) may be incorporated into the channel region, since strained-SiC also has greater carrier mobility characteristics. (Akira Yamada, Tatsuro Watahiki, Shuhei Yagi, Katsuya Abe, and Makoto Konagai, “Epitaxial Growth of Strained Si1-xCx on Si and Its Application to MOSFET,” International Symposium on Quantum Effect Electronics, 2002.)
Formation of a strained-Si layer on a semiconductor wafer has been done in a variety of ways. One technique involves complex fabrication processes, which includes multiple epitaxial growth steps. For example, a relatively thick, graded buffer silicon-germanium (SiGe) film 100 is epitaxially grown onto a silicon, or semiconductor, substrate 102, followed by epitaxial growth of a relaxed SiGe film 103 onto the buffer SiGe film 100 and epitaxial growth of a strained-Si layer 104 onto the relaxed SiGe film 103, as shown in FIG. 1. The strain in the strained-Si layer 104 is induced by the underlying SiGe films 100 and 103. The buffer SiGe film 100 is typically formed with a graded concentration of Ge in the Si, wherein the concentration of the Ge is slowly increased as the buffer SiGe film 100 is grown on the substrate 102. In order to produce high quality strained-Si it is essential to carefully control the stoichiometry of the layer during the SiGe epitaxial growth process. Thus, the introduction of the gases into the epitaxial growth reactor chamber (not shown) must be carefully varied during fabrication of the buffer SiGe film 100. In this manner, the spacing between the atoms in the crystalline structure of the buffer SiGe film 100 is slowly increased from the beginning 106 to the surface 108 of the buffer SiGe film 100. When the relaxed SiGe film 103 and the Si layer 104 are epitaxially grown on top of the buffer SiGe film 100, the increased spacing is effectively maintained between the Si atoms which leads to a straining of the Si layer 104.
A conventional CMOS device 110, having a conventional gate oxide region 118 and conventional source, drain and gate electrodes 112, 114 and 116, is then fabricated on top of the strained-Si layer 104. The increased spacing between the Si atoms in the strained-Si layer 104 enhances the mobility of the carriers in the channel region, which is formed in the strained-Si layer 104 under the gate oxide 118 and between the source and drain 112 and 114.
The presence of the strained-Si layer 104 sets limitations on the temperatures at which any subsequent processing steps may be performed, thereby limiting the flexibility with which the subsequent processing steps may be performed. Furthermore, the relatively thick SiGe film 100 acts as a thermal insulation layer, so the CMOS devices formed thereon are susceptible to self-heating during operation of the IC, thereby degrading the performance capability of the IC. Also, isolation of the CMOS device 110, typically with shallow trench isolation, must be defined in both the strained-Si layer 104 and the SiGe films 100 and 103 as well as in the silicon substrate 102, which adds to the complexity of the overall IC fabrication. Furthermore, this technique is prone to defects, which may occur in the SiGe films 100 and 103 and, thus, propagate into the strained-Si layer 104 and higher layers of materials. Such defects may involve threading dislocations in the crystalline structure of the various layers as well as “misfit” dislocations at the interface between the relaxed SiGe film 103 and the strained-Si layer 104. The dislocations, as well as precipitates nucleated at the dislocation core area, negatively impact carrier mobility, gate oxide quality and overall device performance.
The use of the strained-SiC film in the channel region of the CMOS device 110, as shown in FIG. 2, may be simpler than the strained-Si technique described above. An epitaxial growth process is performed to grow a crystalline SiC film 120 on the silicon substrate 102. Since carbon is a smaller atom than silicon, the presence of the carbon in the SiC film 120 induces a tensile strain in the crystalline lattice of the SiC film 120 due to the underlying silicon substrate 102, which enhances the mobility of the carriers therein. The CMOS transistor 110, having the source, drain and gate electrodes 112, 114 and 116 and the gate oxide region 118, is then fabricated on top of the strained-SiC layer 120, with the gate oxide region 118 being deposited onto the epitaxially grown SiC film 120.
Neither of these carrier-mobility-improvement techniques compensates for the problems that arise in the use of the suggested higher-K dielectric materials for the gate oxide region 118. In particular, the inferior interface between the gate oxide region 118 and adjacent layers remains a significant issue for the CMOS processing. Special care must be taken in the formation of the gate oxide region 118 and in many subsequent processes. Additionally, the strained-Si layer 104 sets limitations on the temperatures at which any subsequent processing steps may be performed, thereby limiting the flexibility with which the subsequent processing steps may be performed. Therefore, the resulting over-all fabrication is quite complex, time-consuming and costly.
It is with respect to these and other considerations that the present invention has evolved.